Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 19. ADCCON (Write)
BIT NAME
X
DATA BIT
D15–D12
RESET STATE
X
Don’t care.
FUNCTION
Set to 1 to command continuous ADC conversions. The ADCMON bit in
the hardware configuration register must be to set to 1 to load ADC
results into the FIFO. Continuous conversions are only applicable in clock
CONCONV
D11
0
modes 00 and 01. When CONCONV is set to 1, the ADC continuously
converts the channels selected by the ADC conversion register using the
conversion mode selected by the CKSEL1/CKSEL0 bits. Results are
accumulated in the FIFO. Empty the FIFO quickly enough to prevent
overflow conditions.
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
Set to 1 to convert the ADCIN2 voltage in the next ADC conversion cycle.
Set to 1 to convert the GATE2 voltage in the next ADC conversion cycle.
Also, the PD2-3 bit in the shutdown register must be set to 0.
Set to 1 to convert the channel 2 DAC code in the next ADC conversion
cycle.
Set to 1 to convert the channel 2 sense voltage in the next ADC
conversion cycle.
Set to 1 to convert the channel 2 external temperature-sensor
measurement in the next ADC conversion cycle.
Set to 1 to convert the ADCIN1 voltage in the next ADC conversion cycle.
Set to 1 to convert the GATE1 voltage in the next ADC conversion cycle.
Also, the PD1-3 bit in the shutdown register must be set to 0.
Set to 1 to convert the channel 1 DAC code in the next ADC conversion
cycle.
Set to 1 to convert the channel 1 sense voltage in the next ADC
conversion cycle.
Set to 1 to convert the channel 1 external temperature sensor
measurement in the next ADC conversion cycle.
Set to 1 to convert the internal temperature sensor measurement in the
next ADC conversion cycle.
For maximum accuracy, power up all internal blocks
prior to a calibration (MAX11014). The MAX11015 does
not require the current-sense amplifier to be powered
up for a calibration.
LDAC (Write)
Write to the software load DAC register to load the val-
ues stored in the DAC input registers to their respective
DAC output registers. Set the command byte to 66h to
write to the software load DAC register. See Table 21.
Bits D15–D2 are don’t care.
Set the DACCH2 bit, D1, to 1 to load the channel 2
DAC output register with the value stored in the chan-
nel 2 DAC input register. Set the DACCH1 bit, D0, to 1
to load the channel 1 DAC output register with the
value stored in the channel 1 DAC input register. See
Figure 20.
46
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